Constructing augmented time compactors

In this paper, a procedure for constructing time compactors based on a new 3-dimensional augmented product code is presented. Accordingly, augmented time compactors are constructed by assigning a unique triplet <;x, y, z> to each scan chain and calculating at least four sets of parity check bits. Each set of parity check bits is attached to one or more multi-input shift registers (MISRs). The proposed procedure allows an efficient construction for different classes of time compactors as well optimization and comparison of their properties. The constructed augmented time compactors demonstrate an ability to achieve a much higher compaction ratio than convolutional and modular compactors.