DocumentCode :
3054089
Title :
Extending Low-Cost Test Signal Synthesis to 40 Gbps
Author :
Keezer, D.C. ; Gray, C.E.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
2011
fDate :
16-18 May 2011
Firstpage :
64
Lastpage :
66
Abstract :
We recently demonstrated two methods for synthesizing 20-24 Gbps test signals using relatively low-cost (off-the-shelf) components [1,2,3]. In the present paper we apply a similar strategy for generating 40 Gbps signals. Our first attempt used the original XOR circuit to combine two 20 Gbps signals. While the internal logic succeeded in producing 40 Gbps, the XOR device output signal was bandwidth-limited and the result was not sufficient for most testing purposes. However, by substituting a newly-released 45 Gbps XOR gate [4], we were able to produce much better quality signals. This paper describes the logic used in this method, and shows the experimental results obtained at 40 Gbps.
Keywords :
logic gates; signal synthesis; XOR gate; bandwidth-limited output signal; bit rate 20 Gbit/s to 24 Gbit/s; bit rate 40 Gbit/s; bit rate 45 Gbit/s; extending low-cost test signal synthesis; Clocks; Jitter; Logic gates; Oscilloscopes; Silicon germanium; Testing; Timing; ATE; high-speed digital test; multigigahertz jitter; multiplexing; picosecond; transmitter;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2011 IEEE 17th International
Conference_Location :
Santa Barbara, CA
Print_ISBN :
978-1-4577-1144-2
Type :
conf
DOI :
10.1109/IMS3TW.2011.37
Filename :
6132739
Link To Document :
بازگشت