Error Prevention, Detection and Diffusion Algorithms for Cryptographic Hardware

It is well known that hardware is susceptible to variety of different faults causing device malfunction, errors in the output or simply destroying the device. These threats refer to any type of hardware. However in case of cryptographic devices, such as smart cards or crypto-processors, errors may also leak some secret information hidden in the device (e.g. encryption keys). This was presented for almost all cryptographic protocols and algorithms allowing an adversary to perform a fault analysis. Therefore it is urgent to propose hardware implementation of cryptographic algorithms that will be immune to this type of attack. Some solutions to this problem have been already proposed for the RSA algorithm based on the Chinese Reminder Theorem and for symmetric algorithms. On the other hand there is a large number of algorithms that are susceptible to fault analysis but no solutions to increase immunity have been proposed so far.