Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs

Interconnect imperfections have become an issue in modern nanometer technologies. Some of them cause Small Delay Defects (SDDs) which are difficult to detect. Furthermore, those SDDs not detected during testing may pose a reliability problem. Nanometer issues (e.g. process variations, spatial correlations) represent important challenges for traditional delay test methods. In this paper, a technique to compute the probability of detection of resistive opens causing SDDs considering process variations is proposed. This technique is used to estimate the Statistical Fault Coverage (SFC) of a circuit. In order to estimate the SFC of a circuit, the delays are propagated using statistical timing analysis, and the analyzed space of possible delay fault locations is obtained using stratified sampling techniques. This methodology is applied to some ISCAS benchmark circuits. The obtained results show the feasibility of the proposed methodology. Measures can be taken for those circuits presenting non-acceptable fault coverage in order to improve their test quality.