A transient error tolerant self-timed asynchronous architecture

High runtime failure rate as a result of reliability detractors is one of the major challenges for scaled-CMOS as well as emerging nanotechnologies. This results in multiple faults during life time operation. In this paper we propose a self-timed asynchronous architecture which can tolerate multiple transient bit-flips. This architecture has self-timed property, making it robust against delay variations caused by increased process variations at nanoscale. The proposed architecture can achieve 100% tolerance of single transient faults as well as more than 93% tolerance of multiple faults for failure rate less than 10^-2.