A transient error tolerant self-timed asynchronous architecture

Author

Zamani, Masoud ; Tahoori, Mehdi B.

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

fYear

2010

fDate

24-28 May 2010

Firstpage

88

Lastpage

93

Abstract

High runtime failure rate as a result of reliability detractors is one of the major challenges for scaled-CMOS as well as emerging nanotechnologies. This results in multiple faults during life time operation. In this paper we propose a self-timed asynchronous architecture which can tolerate multiple transient bit-flips. This architecture has self-timed property, making it robust against delay variations caused by increased process variations at nanoscale. The proposed architecture can achieve 100% tolerance of single transient faults as well as more than 93% tolerance of multiple faults for failure rate less than 10^-2.

Keywords

CMOS integrated circuits; asynchronous circuits; integrated circuit reliability; nanoelectronics; transient analysis; asynchronous circuits; delay variations; multiple transient bit-flips; nanotechnology; reliability detractors; scaled-CMOS integrated circuit; single transient faults; transient error tolerant self-timed asynchronous architecture; Asynchronous circuits; Circuit faults; Circuit noise; Clocks; Computer architecture; Crosstalk; Delay; Robustness; Synchronization; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ETS), 2010 15th IEEE European

Conference_Location

Praha

ISSN

1530-1877

Print_ISBN

978-1-4244-5834-9

Electronic_ISBN

1530-1877

Type

conf

DOI

10.1109/ETSYM.2010.5512777

Filename

5512777