DocumentCode
3054285
Title
Block-based image processor for memory efficient MPEG video decoding
Author
Haoping Yu ; Canfield, B. ; Beyers, B. ; Wai-Man Lam
Author_Institution
Thomson Corp. Res., Indianapolis, IN, USA
fYear
1999
fDate
22-24 June 1999
Firstpage
114
Lastpage
115
Abstract
The block-based image processor, implemented in an HD MPEG-IC for memory reduction, is described. It provides dual compression modes and enables full decoding and display of all 18 ATSC video formats with only 64 or 32 Mbits memory.
Keywords
code standards; data compression; decoding; digital signal processing chips; digital storage; high definition television; telecommunication standards; video coding; 32 Mbit; 64 Mbit; ATSC video formats; HD MPEG-IC; block-based image processor; display; dual compression modes; memory efficient MPEG video decoding; memory reduction; Consumer electronics; Decoding; Displays; High definition video; Image coding; Image edge detection; Image storage; Quantization; Transform coding; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 1999. ICCE. International Conference on
Conference_Location
Los Angeles, CA, USA
Print_ISBN
0-7803-5123-1
Type
conf
DOI
10.1109/ICCE.1999.785192
Filename
785192
Link To Document