DocumentCode
3054355
Title
A cost effective MPEG-2 HDTV system and video decoder IC with integrated down decoder, graphics and display processor
Author
Da Graca, P. ; Duardo, O. ; Hosotani, S. ; Sugawa, S. ; Hong Jiang
Author_Institution
Mitsubishi Electr.-ITA Adv. TV Lab., New Providence, NJ, USA
fYear
1999
fDate
22-24 June 1999
Firstpage
122
Lastpage
123
Abstract
A highly integrated second generation HDTV IC that supports MPEG-2, ATSC, BS4, and other standards is presented. It performs transport stream demultiplexing, video decoding, down conversion for 480I/P displays, display processing and 2D graphics. A full resolution output is provided for HDTV displays.
Keywords
CMOS digital integrated circuits; decoding; demultiplexing equipment; digital signal processing chips; digital television; high definition television; television receivers; television standards; 0.25 micron; 2D graphics; 480I/P display; ATSC; BS4; TV receivers; cost effective MPEG-2 HDTV system; display processing; display processor; full resolution output; highly integrated second generation HDTV IC; integrated down conversion; standards; transport stream demultiplexing; video decoder IC; Costs; Decoding; Filters; Graphics; HDTV; High definition video; SDRAM; Streaming media; Transform coding; Two dimensional displays;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 1999. ICCE. International Conference on
Conference_Location
Los Angeles, CA, USA
Print_ISBN
0-7803-5123-1
Type
conf
DOI
10.1109/ICCE.1999.785196
Filename
785196
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