DocumentCode
3054434
Title
A Concurrent Testing Technique for Analog-to-Digital Converters
Author
Geurkov, Vadim ; Kirischian, Lev
Author_Institution
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada
fYear
2011
fDate
16-18 May 2011
Firstpage
133
Lastpage
136
Abstract
Compaction methods have been successively used for off-line testing of both digital and analog circuits as well as on-line (concurrent) testing of digital circuits. In this work, we extend the use of compaction methods for concurrent testing of analog-to-digital converters. We estimate tolerance bounds for the result of compaction and evaluate the aliasing rate.
Keywords
analogue-digital conversion; integrated circuit testing; analog circuits; analog-to-digital converters; compaction; concurrent testing; digital circuits; off-line testing; on-line testing; tolerance bounds; Accuracy; Built-in self-test; Circuit faults; Compaction; Quantization; Uncertainty; analog-to-digital converter; built-in self-test; concurrent test; signature analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2011 IEEE 17th International
Conference_Location
Santa Barbara, CA
Print_ISBN
978-1-4577-1144-2
Type
conf
DOI
10.1109/IMS3TW.2011.20
Filename
6132753
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