• DocumentCode
    3054505
  • Title

    Placement Optimization of Flexible TFT Digital Circuits

  • Author

    Liu, Wei-Hsiao ; Ma, En-Hua ; Wei, Wen-En ; Li, James Chien-Mo

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2011
  • fDate
    16-18 May 2011
  • Firstpage
    149
  • Lastpage
    152
  • Abstract
    Flexible thin-film transistor (TFT) technology has many advantages over conventional silicon technology such as low cost and short manufacturing time. As the technology advances, large-scale digital circuits can now be implemented using flexible TFT technology. However, transistor mobility changes significantly when TFT are bent, and thus the circuit timing is seriously degraded. A placement optimization of flexible TFT digital circuits is proposed to reduce the timing degradation due to bending effect. Three optimization modes are supported based on different package and bending assumption. So far as we know, this is the first design for flexibility EDA tool.
  • Keywords
    circuit optimisation; digital circuits; flexible electronics; logic gates; thin film transistors; bending effect; flexibility EDA tool; flexible TFT digital circuit; flexible thin-film transistor technology; logic gates; placement optimization; timing degradation; Delay; Libraries; Logic gates; Optimization; Organic thin film transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2011 IEEE 17th International
  • Conference_Location
    Santa Barbara, CA
  • Print_ISBN
    978-1-4577-1144-2
  • Type

    conf

  • DOI
    10.1109/IMS3TW.2011.39
  • Filename
    6132756