Title :
A LOG-EXP still image compression chip design
Author :
Sheng-Chieh Huang ; Liang-Gee Chen
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In this paper, a fully pipelined single chip is proposed for LOG-EXP still image compression. The design of the LOG-EXP image compression focuses on the high compression ratio of a complex texture (e.g. benchmark image baboon) and high quality image, especially the PSNR requirement above 36. In comparison with the JPEG compression result (bpp=0.99, PSNR=26.9), this compression algorithm uses less bpp (bpp=0.87) to get a higher image quality (PSNR=36.38) for the benchmark image baboon. The entire LOG-EXP image compression system can be implemented on a single chip to yield a clock rate of 175 MHz which allow an input rate of 30 frames per second for 1024/spl times/1024 color images.
Keywords :
codecs; data compression; digital signal processing chips; image coding; image colour analysis; integrated circuit design; pipeline processing; 175 MHz; LOG-EXP still image compression chip design; clock rate; color images; complex texture; compression ratio; fully pipelined single chip; high quality image; image quality; input rate; Algorithm design and analysis; Chip scale packaging; Counting circuits; Image coding; Image quality; PSNR; Pixel; Transform coding; Video compression; Videoconference;
Conference_Titel :
Consumer Electronics, 1999. ICCE. International Conference on
Conference_Location :
Los Angeles, CA, USA
Print_ISBN :
0-7803-5123-1
DOI :
10.1109/ICCE.1999.785210