A low power 20GHz RF CMOS based phase-locked loop

The fast growing wireless communication systems have brought on a constant demand for low cost, low power and highly-integrated portable devices. In response to the evolution, the research and development of RF integrated circuits using low cost CMOS processes has been increased dramatically. A phase-locked loop (PLL) is a negative feedback control system which generates a signal with fixed phase and frequency to a reference input. It has wide applications in radio, telecommunication and computer manufacture. Many groups have made efforts on designing high frequency phase locked loops used for low power wireless communication systems. This paper focuses on the development of a low power microwave frequency PLL and its application as a frequency demodulator in a binary frequency shift keying (BFSK) receiver. The input signal is amplified by the low noise amplifier (LNA) and serves as the reference. The PLL tracks the frequency information of the reference input and the amplifier outputs the demodulated signal in digital form.