A Review of First Level Interconnect Modeling Methodology

The paradigm shifts within the microelectronics industry, such as the introduction of highly fragile low-k dielectric films and the shift to lead-free solders, have introduced a host of highly localized thermo-mechanical packaging stress issues. One of these issues is the impact of packaging stresses on low-K inter-layer dielectric (ILD) materials in the die backend. With increasing design complexity, conventional numerical analysis methodologies are proving ineffective in providing a reasonable risk assessment and design improvement strategy. New design tools and methodologies are being aggressively developed for the accurate representation of localized regions of the interconnect and the substrate to determine the level of package-induced stress on the die backend. This paper reviews modeling methodologies particularly relating to ILD delamination and the continuing progression in developing further understanding of the failure mechanisms.