VLSI implementation considerations for turbo decoding using a low latency log-MAP

Author

Raghupathy, A. ; Liu, K.J.R.

Author_Institution

Qualcomm Inc., San Diego, CA, USA

fYear

1999

fDate

22-24 June 1999

Firstpage

182

Lastpage

183

Abstract

The soft-output Viterbi (see IEEE J. Sel. Areas in Comm., vol.16, p.260-4, 1998) algorithm (SOVA) and the log-maximum a posterior probability (log-MAP) algorithm are commonly used in turbo decoding. We propose to modify the sliding window MAP-algorithm of Viterbi to reduce the computational delay even further. We compare the simulation performance of this low latency log-MAP algorithm with the sliding window log-MAP. We also estimate the VLSI implementation complexities of the SOVA, the log-MAP and the proposed low latency log-MAP.

Keywords

VLSI; Viterbi decoding; computational complexity; delays; maximum likelihood decoding; turbo codes; SOVA; VLSI implementation complexities; computational delay reduction; log-MAP algorithm; log-maximum a posterior probability algorithm; low latency log-MAP; low latency log-MAP algorithm; simulation performance; sliding window MAP-algorithm; sliding window log-MAP; soft-output Viterbi algorithm; turbo decoding; Additive white noise; Computational modeling; Delay; Fading; Gaussian noise; Hardware design languages; Iterative decoding; Noise figure; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 1999. ICCE. International Conference on

Conference_Location

Los Angeles, CA, USA

Print_ISBN

0-7803-5123-1

Type

conf

DOI

10.1109/ICCE.1999.785223

Filename

785223