Title :
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
Author :
Chang, Jonathan T Y ; McCluskey, Edward J.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
fDate :
27 Apr-1 May 1997
Abstract :
A stress procedure for reliability screening, SHOrt Voltage Elevation (SHOVE) test, is analyzed here. During SHOVE, test vectors are run at higher-than-normal supply voltage for a short period. Functional tests and IDDQ tests are then performed at the normal voltage. This procedure is effective in screening oxide thinning, which occurs when the oxide thickness of a transistor is less than expected, as well as via defects. The stress voltage of SHOVE testing should be set such that the electric field across an oxide is approximately 6MV/cm. The stress time can be calculated by using the “effective oxide thinning” model. We will also discuss the requirements on input vectors for stressing complementary CMOS logic gates and CMOS domino logic gates efficiently
Keywords :
CMOS integrated circuits; integrated circuit reliability; integrated circuit testing; CMOS IC; IDDQ test; SHOVE test; complementary logic gate; domino logic gate; functional test; oxide thinning; reliability screening; short voltage elevation test; transistor; via defect; voltage stress; CMOS logic circuits; Circuit testing; Costs; Integrated circuit testing; Logic gates; Performance evaluation; Pollution measurement; Stress; Temperature; Voltage;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.600331
