A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems

This paper presents an ultra low-power SAR ADC in 0.18 μm CMOS technology for epileptic seizure detection applications. The ADC is powered by a single supply voltage of both analog and digital circuits to avoid using the level-shifters. A latched comparator is used to quickly generate the comparison results while consuming no DC current. Split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. A smaller-than-unit capacitor is used at the end of the least significant bit array to mitigate the negative impact of the parasitic components on the linearity of the capacitors array. As a result, both DNL/INL and SNDR of the ADC is improved. Our post-layout simulation shows that at 1 V supply, 1 kS/s the proposed SAR archives 8.7 ENOB while consuming only 9.87 nW. This yields an FOM of 23.7 fJ/conversion-step. Its leakage power consumption is 1.46 nW.