A novel quantization algorithm suitable for high-speed analog-to-digital converters

Author

Soufizadeh-Balaneji, N. ; Hadidi, Khayrollah

Author_Institution

Electr. Eng. Dept., Urmia Univ., Urmia, Iran

fYear

2012

fDate

2-5 Dec. 2012

Firstpage

25

Lastpage

28

Abstract

A novel quantization algorithm capable of being employed in high-resolution high-speed ADCs is described. In order to verify the efficiency of proposed architecture a 3.3-V 10-bit ADC with roughly 67-dB spurious free dynamic range (SFDR) and 59-dB signal-to-noise-and-distortion ratio (SNDR) has been reported. The converter designed in standard 0.35-μm CMOS technology consumes 156 mW from a nominal supply voltage when it operates at a sampling rate of 80-Msample/s.

Keywords

CMOS integrated circuits; distortion; high-speed integrated circuits; integrated circuit design; quantisation (signal); CMOS technology; SFDR; SNDR; architecture; converter design; high-resolution high-speed ADC; high-speed analog-to-digital converter; noise figure 59 dB; noise figure 67 dB; power 156 mW; quantization algorithm; signal-to-noise-and-distortion ratio; size 0.35 mum; spurious free dynamic range; voltage 3.3 V; word length 10 bit; Analog-digital conversion; CMOS integrated circuits; Calibration; Clocks; Pipelines; Quantization; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1728-4

Type

conf

DOI

10.1109/APCCAS.2012.6418962

Filename

6418962