A DT 0–2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity

Author

Tao He ; Yun Du ; Yang Jiang ; Sai-Weng Sin ; Seng-Pan, U. ; Martins, Rui P.

Author_Institution

State-Key Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China

fYear

2012

fDate

2-5 Dec. 2012

Firstpage

33

Lastpage

36

Abstract

This paper presents a new structure of the discrete time 0-2 MASH sigma-delta modulator implemented with VCO-based quantizer in the second stage. The proposed scheme enhances the linearity of the VCO based quantizer, meanwhile it takes advantage of the intrinsic DEM function and first order noise shaping in the second stage. Besides, the matching requirement is relaxed and the digital canceling filter is largely simplified. Moreover, no additional active adder in or between two stages is needed because of the 0-2 MASH structure, which can save a lot of power. The proposed DT 0-2 MASH sigma-delta (ΣΔ) modulator with 10MHz signal bandwidth for wideband applications is designed and simulated in Matlab. The performance of the modulator can reach 97dB SND Runder a sampling rate of 1.15GHz.

Keywords

adders; digital filters; integrated circuit noise; modulators; quantisation (signal); sampling methods; sigma-delta modulation; voltage-controlled oscillators; 0-2 MASH structure; DEM function; DT 0-2 MASH ΣΔ modulator; Matlab; SND Runder; VCO-based quantizer; active adder; digital canceling filter; discrete time 0-2 MASH sigma-delta modulator; first order noise shaping; frequency 1.15 GHz; frequency 10 MHz; linearity; matching requirement; noise figure 97 dB; sampling rate; signal bandwidth; wideband application; Bandwidth; Linearity; Modulation; Multi-stage noise shaping; Noise; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1728-4

Type

conf

DOI

10.1109/APCCAS.2012.6418964

Filename

6418964