Si nanowire MOSFET with gate-all-around electrode

In this work, a top-down approach has been adopted for the first-time to pattern single-crystalline Si NW on SOI substrates using planar technology processes. The two critical parameters of the nanowire are defined by the thickness of Si active layer and the width of a masking spacer. The NW has an elliptical cross-section having a semimajor axis less than 150 nm and the semiminor axis depending on process conditions. A complete mask set has been developed for the NW-MOSFET defining mesa island on Si and channel area length.