Title :
Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM
Author :
Shao-Cheng Wang ; Geng-Cing Lin ; Yi-Wei Lin ; Ming-Chien Tsai ; Yi-Wei Chiu ; Shyh-Jye Jou ; Ching-Te Chuang ; Nan-Chun Lien ; Wei-Chiang Shih ; Kuen-Di Lee ; Jyun-Kai Chu
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps ~ 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 ~ 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.
Keywords :
CMOS memory circuits; SRAM chips; frequency dividers; oscillators; CMOS 6T SRAM; Skitter based structure; UMC standard performance CMOS technology; all-digital monitor structure; dynamic word-line pulse write margin monitor; dynamic write margin characterization; frequency divider based structure; memory size 256 KByte; memory size 6 TByte; ring oscillator; size 55 nm; write margin measurement; Delay; Frequency conversion; Frequency measurement; Logic gates; Pulse measurements; Random access memory; Ring oscillators;
Conference_Titel :
Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4577-1728-4
DOI :
10.1109/APCCAS.2012.6418985
