Title :
Low power delay locked loop with all digital controlled SAR delay cell
Author :
Ko-Chi Kuo ; Chung-Yuan Chang ; Si-Hsien Li
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan
Abstract :
A delay-locked loop (DLL) with the successive approximation register (SAR) circuit is proposed to achieve fast locking effect. In order to lower the power consumption, a loop state controller (LSC) is proposed. When the loop is locked, the path which goes through the register is chosen to enter the sleeping mode, and disable part of the circuit in the power saving mode. When entering the sleeping mode, the register provides the fixed input code; the phase error comparator (PEC) keeps tracking process, voltage, temperature, and load (PVTL) variation. Once a variation is occurred, the PEC sends a signal to the loop state controller (LSC) and enables the circuit from the sleeping mode to tracking mode when the clock needs to be locked again. The proposed DLL only needs 6 cycles to lock again. The simulated locking range is from 150MHz to 900MHz in the TSMC 0.18μm process. The power consumptions are 15mW in locking mode and 9mW in sleeping modes.
Keywords :
CMOS integrated circuits; comparators (circuits); delay lock loops; low-power electronics; LSC; PEC; all digital controlled SAR delay cell; frequency 150 MHz to 900 MHz; locking effect; loop state controller; low power delay locked loop; phase error comparator; power 15 mW; power 9 mW; power saving mode; size 0.18 mum; sleeping mode; successive approximation register; tracking mode; Clocks; Delay; Delay lines; Detectors; Logic gates; Registers; Synchronization;
Conference_Titel :
Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4577-1728-4
DOI :
10.1109/APCCAS.2012.6418986
