DocumentCode
3056096
Title
A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation
Author
Yiwen Zhang ; Xiaoshi Zhu ; Chixiao Chen ; Fan Ye ; Junyan Ren
Author_Institution
State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear
2012
fDate
2-5 Dec. 2012
Firstpage
128
Lastpage
131
Abstract
Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters (TIADCs). A calibration method implemented in mixed circuits with low-complexity and fast-convergence is proposed in this paper. The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals. The detected sample-time error is corrected by a voltage-controlled sampling switch. Experimental result of the 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise-and-distortion ratio improves 19.1 dB, and the spurious-free dynamic range improves 34.6 dB for a 70.12-MHz input after calibration. The convergence time of calibration is about 20000 sampling intervals.
Keywords
analogue-digital conversion; correlation methods; error detection; mixed analogue-digital integrated circuits; correlation-based detection; mixed circuits; sample-time error calibration technique; sample-time error detection; signal-to-noise-and-distortion ratio; time-interleaved ADC; time-interleaved analog-to-digital converters TIADC; voltage-controlled compensation; Calibration; Clocks; Convergence; Correlation; Signal resolution; Switches; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on
Conference_Location
Kaohsiung
Print_ISBN
978-1-4577-1728-4
Type
conf
DOI
10.1109/APCCAS.2012.6418988
Filename
6418988
Link To Document