High performance picture-in-picture (PIP) IC using embedded DRAM technology

Author

Brett, M. ; Wendel, D.

Author_Institution

Semicond. Group, Siemens AG, Munich, Germany

fYear

1999

fDate

22-24 June 1999

Firstpage

342

Lastpage

343

Abstract

In the paper the next generation of a low cost, high performance single-chip picture-in-picture IC is presented. This chip will be produced in a 0.35 /spl mu/m eDRAM technology and integrates a digital multistandard color decoder, embedded DRAM, A/D and D/A converter and a data slicer for caption services. The paper deals with the digital video signal processing for color decoding with asynchronous sampling and the compensation of the skew. A new algorithm for a jointline-free true frame display is developed. The chip allows a smooth scaling from 1/81 to 1/4 of full screen picture size and implements a data compression algorithm for split-screen modes.

Keywords

CMOS digital integrated circuits; consumer electronics; decoding; digital signal processing chips; image colour analysis; image sampling; television receivers; video signal processing; 0.35 micron; A/D converter; D/A converter; PIP IC; asynchronous sampling; caption services; color decoding; compensation; data compression algorithm; data slicer; digital multistandard color decoder; digital video signal processing; embedded DRAM technology; high performance picture-in-picture IC; jointline-free true frame display; skew; smooth scaling; split-screen modes; Clocks; Color; Decoding; Filters; Frequency synchronization; Phase locked loops; Random access memory; Sampling methods; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 1999. ICCE. International Conference on

Conference_Location

Los Angeles, CA, USA

Print_ISBN

0-7803-5123-1

Type

conf

DOI

10.1109/ICCE.1999.785391

Filename

785391