A small die area and high linearity 10-bit capacitive three-level DAC

Author

Oshiro, K. ; Kanemoto, Daisuke ; Kanaya, Haruichi ; Pokharel, R. ; Yoshida, Kenta

Author_Institution

Grad. Sch. of Inf. Sci. & Electr. Eng., Kyushu Univ., Fukuoka, Japan

fYear

2012

fDate

2-5 Dec. 2012

Firstpage

164

Lastpage

167

Abstract

A 10-bit capacitive three-level digital-to-analog converter (TLDAC) is provided to reduce differential non-linearity (DNL) and integral non-linearity (INL) caused by capacitive mismatch. The simulation results of binary-weighted TLDAC show 50 % reduction in DNL and INL compared to conventional binary-weighted DAC. Furthermore an additional reference voltage source has been reduced due to the advantages of differential circuit. The proposed 10-bit differential TLDAC was implemented in 0.18 μm CMOS process and its total area is 0.081 mm².

Keywords

CMOS integrated circuits; active networks; digital-analogue conversion; reference circuits; CMOS process; DNL; INL; additional reference voltage source; binary-weighted TLDAC; capacitive mismatch; capacitive three-level DAC; capacitive three-level digital-to-analog converter; conventional binary-weighted DAC; die area; differential TLDAC; differential circuit; differential nonlinearity; integral nonlinearity; size 0.18 mum; word length 10 bit; Arrays; Capacitors; Decoding; Linearity; Power demand; Solid state circuits; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1728-4

Type

conf

DOI

10.1109/APCCAS.2012.6418997

Filename

6418997