Title :
Hardware implementations of hash function Luffa
Author :
Satoh, Akashi ; Katashita, Toshihiro ; Sugawara, Takeshi ; Homma, Naofumi ; Aoki, Takafumi
Author_Institution :
Res. Center for Inf. Security, Nat. Inst. of Adv. Ind. Sci. & Technol., Tokyo, Japan
Abstract :
This paper presents hardware architectures for the hash algorithm Luffa, which is a candidate for the next-generation hash standard SHA-3. The architectures were implemented by using a 90-nm CMOS standard cell library. A high throughput of 35 Gbps for a high-speed architecture and a gate count of 14.7 kgate for a compact architecture were obtained. In comparison with Keccak, other SHA-3 candidate in the sponge function category, as well as with the current hash standard SHA-256, Luffa exhibited the advantage of flexible implementation ranging from high-speed to compact circuits.
Keywords :
CMOS logic circuits; cellular arrays; cryptography; integrated logic circuits; logic arrays; CMOS standard cell library; Keccak; Luffa; SHA-3 hash standard; compact architecture; gate count; hardware architecture; hash function; high speed architecture; sponge function category; CMOS technology; Computer architecture; Cryptography; Digital signatures; Flexible printed circuits; Hardware; Information security; Libraries; NIST; Throughput;
Conference_Titel :
Hardware-Oriented Security and Trust (HOST), 2010 IEEE International Symposium on
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-7811-8
DOI :
10.1109/HST.2010.5513102
