• DocumentCode
    3056328
  • Title

    PC-based DTV architecture

  • Author

    Tran, T. ; Moriarty, M. ; Giang Dao ; Welker, M.

  • Author_Institution
    Adv. Eng., Compaq Comput. Corp., Houston, TX, USA
  • fYear
    1999
  • fDate
    22-24 June 1999
  • Firstpage
    346
  • Lastpage
    347
  • Abstract
    This paper presents the first PC-based DTV architecture using an industry standard PCI bus to transfer decoded video data from a DTV decoder to the graphics subsystem of a multimedia PC. The proposed architecture eliminates: 1) the need for a separate video port cable between a PC-based DTV decoder and a graphics controller, and 2) the need for a nonstandard graphics controller video port. This paper also presents a proprietary method to burst decoded DTV data over the PCI bus with no visible video artifacts due to bus latency or different video/graphics refresh rates. In normal operation, this architecture consumes only about 31% of the bandwidth of a 33 MHz 32-bit PCI bus.
  • Keywords
    digital television; multimedia systems; system buses; 32 bit; 33 MHz; DTV decoder; PC-based DTV architecture; PCI bus; decoded video data; graphics subsystem; multimedia PC; video artifacts; Bandwidth; Buffer storage; Clocks; Computer architecture; Computer graphics; Decoding; Delay; Digital TV; Displays; Logic;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Consumer Electronics, 1999. ICCE. International Conference on
  • Conference_Location
    Los Angeles, CA, USA
  • Print_ISBN
    0-7803-5123-1
  • Type

    conf

  • DOI
    10.1109/ICCE.1999.785394
  • Filename
    785394