DocumentCode :
3056428
Title :
Thermal testing of a 3-die stacked chip scale package including evaluation of simplified and complex package geometry finite element models
Author :
Zahn, Bret A.
Author_Institution :
ChipPAC Inc., Chandler, AZ, USA
fYear :
2004
fDate :
2004
Firstpage :
491
Lastpage :
498
Abstract :
Thermal performance testing was conducted on a 16×16 mm, 2-metal layer, 591-ball, 0.50 mm pitch, 1.20 mm overall height chip scale package (CSP) containing an offset pyramid configuration of three stacked Delco thermal test die. Die sizes from bottom-to-top were 10.16×10.16 mm (Delco PST-6), 6.35×6.35 mm (Delco PST-4), and 3.81×0.81 mm (Delco PST-2). Testing was carried out using eight different multi-die power configurations in a natural convection environment to highlight the effects of radiant and convective heat transfer. Measured data was obtained on a sample size of five packages to calculate Theta JA, Psi JT, and Psi JB values at each of the eight different multi-die power configurations. Furthermore, Theta JC and Theta JB cold plate measurements were also obtained. For the purposes of thermal testing, each of the five CSP test samples was mounted on a JEDEC standard 101.5×114.1×1.60 mm 1S2P thermal test board. Measured results are used to suggest a methodology for the generation of linear superposition matrix equations as a means to present multi-die package thermal test data such that it may account for changes in. thermal cross talk between die at varying die power configurations. The ANSYS finite element analysis modeling software was used to simulate the eight aforementioned thermal test configurations for the purpose of verifying the acquired test data. Both simplified and complex package substrate metal layer trace patterns were evaluated for simulation accuracy. The simplified patterns consisted of conductor traces that do not follow the detailed routing of the actual design, but instead extend straight outward towards the substrate edge. Alternatively, the complex patterns consisted of the detailed trace layers exactly as they are physically routed on the CSP substrate. In both the complex and simplified metal layer trace pattern finite element models, vias that connect the top and bottom trace layers were represented by two-dimensional thermal conduction elements. Simulated results for both the simplified and complex metal layer trace pattern models are compared to the acquired test data. The CSP package structure, thermal test data, and finite element models are presented and discus- sed.
Keywords :
chip scale packaging; circuit simulation; cooling; finite element analysis; heat conduction; heat radiation; integrated circuit interconnections; integrated circuit modelling; integrated circuit testing; multichip modules; natural convection; standards; thermal analysis; thermal management (packaging); 0.5 mm; 1.6 mm; 10.16 mm; 101.5 mm; 114.1 mm; 16 mm; 2D thermal conduction elements; 3.81 mm; 6.35 mm; ANSYS finite element analysis modeling software; CSP package structure; CSP test samples; Delco PST-2; Delco PST-4; Delco PST-6; JEDEC standard thermal test board; Psi JB values; Psi JT values; Theta JA values; bottom trace layers; complex package geometry finite element models; conductor traces; convective heat transfer; die sizes; linear superposition matrix equations; metal layer trace pattern finite element models; multi-die package thermal test data; multi-die power configurations; natural convection environment; offset pyramid configuration; package substrate metal layer trace patterns; physically routed trace layers; radiant heat transfer; simplified package geometry finite element models; simulation accuracy; stacked Delco thermal test die; substrate edge; thermal cross talk; thermal performance testing; thermal test configurations; thermal test data; three-die stacked chip scale package; top trace layers; Chip scale packaging; Finite element methods; Geometry; Heat transfer; Power measurement; Pressure measurement; Size measurement; Software testing; Solid modeling; Thermal conductivity;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, 2004. EuroSimE 2004. Proceedings of the 5th International Conference on
Print_ISBN :
0-7803-8420-2
Type :
conf
DOI :
10.1109/ESIME.2004.1304082
Filename :
1304082
Link To Document :
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