A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs

In the layout design of transport-processing FPGAs, it is not only required that routing congestion be kept small but also that circuits implemented on them should operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs, whose objective is to minimize the routing congestion, and proposes a new algorithm, in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on the hierarchical bipartitioning of the layout regions and LUT (lookup table) sets that are to be placed. Each bipartitioning procedure consists of three phases: (1) estimation of path lengths, (2) bipartitioning of a set of terminals, and (3) bipartitioning of a set of LUTs. After searching the paths with tighter path length constraints by estimating the path lengths in (1), phases (2) and (3) are executed so that their path lengths are reduced with higher priority, and thus path length constraints are not violated. The algorithm has been implemented and applied to transport-processing circuits and compared with conventional approaches. The results demonstrate that the algorithm resolves path length constraints for 11 out of 13 circuits, though it increases the routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and reduces the circuit delay by an average of 23%