Anti-tamper JTAG TAP design enables DRM to JTAG registers and P1687 on-chip instruments

Author

Clark, C.J.

Author_Institution

Intellitech Cjclark(at)intellitech(dot)com, USA

fYear

2010

fDate

13-14 June 2010

Firstpage

19

Lastpage

24

Abstract

This paper describes an anti-tamper JTAG Tap design which uses SHA256 secure hash and a true random number generator (TRNG) to create a low gate overhead challenge/response based access system for IC test and on-chip internals. The system may be used to enable 1149.1 TAP instructions or may control access to an IEEE P1687 on-chip instrument. The TAP owner (manufacturer of the IC) may then use DRM (Digital Rights Management) based JTAG software to manage which end users have access to the TAP or TAP accessible areas of the IC.

Keywords

digital rights management; integrated circuit testing; random number generation; IC test; IEEE P1687 on-chip instrument; JTAG registers; JTAG software; SHA256 secure hash; anti-tamper JTAG TAP design; challenge/response based access system; digital rights management; true random number generator; Computer crime; Digital integrated circuits; Embedded system; Field programmable gate arrays; Instruments; Manufacturing; Reverse engineering; System testing; System-on-a-chip; Unmanned aerial vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Hardware-Oriented Security and Trust (HOST), 2010 IEEE International Symposium on

Conference_Location

Anaheim, CA

Print_ISBN

978-1-4244-7811-8

Type

conf

DOI

10.1109/HST.2010.5513119

Filename

5513119