Sub-micron Esaki Tunnel Diode fabrication and characterization

Recently much effort has been made in characterizing and realizing tunneling field effect transistors (TFET). Fundamental to the operation of such devices is the direct band-to-band tunneling of carriers from the n⁺⁺ source to the p⁺⁺ drain, which is the same current transport mechanism of Esaki Tunnel Diodes (ETD). Therefore, ETDs are an effective way to understand the potential of TFETs for high speed, low power applications. Few studies of submicron ETDs have been performed, which is critical for integration of TFETs into modern VLSI/UVLSI circuits. This paper reports on the fabrication and characterization of sub-micron GaAs/InGaAs ETDs on a Si substrate with junction areas below 0.1 ¿m². Using conservative J_p, tunnel junctions of radii below 100 nm have been electrically tested. A semi-log plot of the forward and reverse I-V characteristics is shown. The reverse bias Zener currents show a range of 6 orders of magnitude. The large current devices show negative differential resistance, a result of using a large area ETD as a virtual ground. In the forward bias, peak currents (I_p) range 7 orders of magnitude.