A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology

This paper presents a 12-bit 50-MS/s pipelined SAR analog-to-digital converter (ADC) with loading-separating technique. The proposed loading-separating technique relaxes output loading of multiplying digital-to-analog converter (MDAC) and increases the time budget of bit cycling for the 2^nd stage. In addition, a split-path amplification MDAC is proposed to enhance amplifier´s gain and bandwidth. The ADC core occupies an active area of 0.27 mm² in TSMC 90-nm 1P9M CMOS process. The measured results show that the proposed ADC achieves 63.56 dB SNDR with 2.17 mW power consumption.