Title :
The MorphoSys dynamically reconfigurable system-on-chip
Author :
Lu, Guangming ; Singh, Hartej ; Lee, Ming-Hau ; Bagherzadeh, Nader ; Kurdahi, Fadi J. ; Filho, Eliseu M C ; Alves, Vladimir Castro
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
Abstract :
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity dynamic reconfigurability and considerable depth of programmability. The first implementation of the MorphoSys architecture, the M1 chip, is currently at an advanced stage and it will operate at 100 MHz. Simulation results indicate significant performance improvements for different classes of applications, as compared to general-purpose processors. Meanwhile, MorphoSys can provide the potential hardware platforn for the evolvable hardware (EH) simulation with the help of the software
Keywords :
digital simulation; reconfigurable architectures; reduced instruction set computing; M1 chip; MorphoSys dynamically reconfigurable system-on-chip; RISC processor; evolvable hardware simulation; granularity dynamic reconfigurability; reconfigurable cells array; simulation results; Application software; Application specific integrated circuits; Computer architecture; Field programmable gate arrays; Hip; Programmable logic devices; Reduced instruction set computing; Software performance; System-on-a-chip; Systems engineering and theory;
Conference_Titel :
Evolvable Hardware, 1999. Proceedings of the First NASA/DoD Workshop on
Conference_Location :
Pasadena, CA
Print_ISBN :
0-7695-0256-3
DOI :
10.1109/EH.1999.785447
