A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array

Author

Wen-Lan Wu ; Sai-Weng Sin ; Seng-Pan, U. ; Martins, Rui P.

Author_Institution

State-Key Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China

fYear

2012

fDate

2-5 Dec. 2012

Firstpage

268

Lastpage

271

Abstract

A novel switching method is proposed and implemented in a 10-bit fully differential SAR ADC. When compared with the charge recycling or the set-and-down approach, the proposed scheme uses a single-ended switching procedure to reduce the total switching energy by 80% or 20%, respectively. Besides, two redundant decisions are inserted in the SAR ADC with a 4b/4b/4b configuration, which is capable of more than 30% speed enhancement. The 10-bit SAR ADC´s performance is verified through Matlab simulation and it achieves 10-b resolution. After a Monte-Carlo analysis (100-times), the mean value of the SNDR is 61.8dB, and the maximum INL and DNL are 0.05LSB and 0.1LSB, respectively.

Keywords

Monte Carlo methods; analogue-digital conversion; digital-analogue conversion; switched networks; Matlab simulation; Monte Carlo analysis; SAR ADC; analog-digital converters; charge recycling; digital-analog converters; set-and-down approach; splitted-MSB-cap DAC array; successive approximation register; word length 10 bit; Arrays; Capacitance; Capacitors; Redundancy; Solid state circuits; Switches; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1728-4

Type

conf

DOI

10.1109/APCCAS.2012.6419023

Filename

6419023