DocumentCode
3057122
Title
A unified {2n−1, 2n, 2n+1} RNS scaler with dual scaling constants
Author
Low, Jeremy Yung Shern ; Tay, Thian Fatt ; Chip-Hong Chang
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
fYear
2012
fDate
2-5 Dec. 2012
Firstpage
296
Lastpage
299
Abstract
Scaling is often used to prevent overflow in digital signal processing (DSP). Unfortunately, scaling in residue number system (RNS) consumes significant hardware area and delay. The problem is worsened when more than one scaling factors are needed. Applications in which the computation results fall into two distinct dynamic ranges could benefit from having two scaling factors for better trade-off between precision and hardware savings. This paper presents a new unified architecture for scaling an integer in the three-moduli set {2n-1, 2n, 2n+1} RNS by two different scaling factors, 2n(2n+1) and 2n. The unified architecture has hardware complexity approximating the most compact adder-based RNS scaler for a single scaling constant of 2n. Our analysis shows that the proposed dual scaler design is not only several orders of magnitude smaller but also significantly faster than the fastest LUT-based RNS scalers for the same scaling constants.
Keywords
adders; digital signal processing chips; residue number systems; DSP; LUT-based RNS scalers; adder-based RNS scaler; different scaling factors; digital signal processing; dual scaler design; dual scaling constants; dynamic ranges; hardware area; hardware complexity; hardware savings; residue number system; single scaling constant; three-moduli set; unified architecture; Computer architecture; Delay; Digital signal processing; Hardware; Logic gates; Transistors; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on
Conference_Location
Kaohsiung
Print_ISBN
978-1-4577-1728-4
Type
conf
DOI
10.1109/APCCAS.2012.6419030
Filename
6419030
Link To Document