Title :
Improving correctness of finite-state machine synthesis from multiple partial input/output sequences
Author :
Chongstitvatana, Prabhas ; Aporntewan, Chatchawit
Author_Institution :
Dept. of Comput. Eng., Chulalongkorn Univ., Bangkok, Thailand
Abstract :
Our previous work focused on the synthesis of sequential circuits based on a partial input/output sequence. As the behavioural description of the target circuit is not known the correctness of the result can not be verified. This paper proposes a method which increases the correctness percentage of the finite-state machine (FSM) synthesis using multiple partial input/output sequences. The synthesizer is based on genetic algorithm. The experimental results show that the correctness percentage can be increased to 100% by increasing the number of input/output sequences
Keywords :
finite state machines; formal verification; genetic algorithms; logic design; sequential circuits; behavioural description; correctness; finite-state machine; finite-state machine synthesis; genetic algorithm; multiple partial input/output sequences; sequential circuits; Adders; Circuits; Genetics; Hardware; Humans; Random access memory; Read-write memory; Synthesizers; Table lookup;
Conference_Titel :
Evolvable Hardware, 1999. Proceedings of the First NASA/DoD Workshop on
Conference_Location :
Pasadena, CA
Print_ISBN :
0-7695-0256-3
DOI :
10.1109/EH.1999.785463
