A novel hardware-oriented decoding algorithm for non-binary LDPC codes

This paper presents a novel hardware-oriented decoding algorithm in the log-domain for non-binary LDPC codes over GF(2^m). As for max-log-SPA, only summations and comparisons are required in this new algorithm. During the vertical update, these two operations are divided into layers based on the distribution of variable vectors that satisfy the check function. The number of additions during the vertical update is reduced by a factor of approximately p-2 without a performance loss, where p is the row weight of the parity check matrix.