Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system

Several types of asynchronous bus interface units for AMBA AHB bus are designed so that an OpenGL ES 2.0 vertex shader (VS) processor can communicate with other hardware units of a 3D graphics system via AHB bus working under different frequencies. We consider the data-write and data-read operations separately for the VS functioning as a master or as a slave. The first types AHB wrapper design is direct implementation of the required AHB interface signals. The second and third types of wrapper designs are based on the implementation of Open Core Protocol (OCP) interface signals. We have made comparisons of different implementations for both single mode and burst mode bus transactions. The multi-clock domain wrapper design has been used in the design of a 3D graphics SoC and has been verified on FPGA board.