Title :
Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system
Author :
Shen-Fu Hsiao ; Chi-Guang Lin ; Po-Han Wu ; Chia-Sheng Wen
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan
Abstract :
Several types of asynchronous bus interface units for AMBA AHB bus are designed so that an OpenGL ES 2.0 vertex shader (VS) processor can communicate with other hardware units of a 3D graphics system via AHB bus working under different frequencies. We consider the data-write and data-read operations separately for the VS functioning as a master or as a slave. The first types AHB wrapper design is direct implementation of the required AHB interface signals. The second and third types of wrapper designs are based on the implementation of Open Core Protocol (OCP) interface signals. We have made comparisons of different implementations for both single mode and burst mode bus transactions. The multi-clock domain wrapper design has been used in the design of a 3D graphics SoC and has been verified on FPGA board.
Keywords :
asynchronous circuits; clocks; field programmable gate arrays; integrated circuit design; logic design; microprocessor chips; system-on-chip; three-dimensional integrated circuits; 3D graphics SoC; 3D graphics system; AHB interface signals; AHB wrapper design; AMBA AHB bus; FPGA board; OpenGL ES 2.0 vertex shader processor; asynchronous AHB bus interface designs; asynchronous bus interface units; burst mode bus transactions; hardware units; multi-clock domain wrapper design; multiple-clock-domain graphics system; open core protocol interface signals; single mode bus transactions; Clocks; Graphics; Hardware; IP networks; Logic gates; Synchronization; Throughput; AMBA AHB; Bus interface unit; OpenGL ES; asynchronous wrapper; multiple clock domains;
Conference_Titel :
Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4577-1728-4
DOI :
10.1109/APCCAS.2012.6419058
