A post-processing scan-chain watermarking scheme for VLSI intellectual property protection

Preprocessing approaches at various design abstraction levels have been widely studied among the constraint-based watermarking schemes proposed to protect VLSI intellectual property (IP). Post-processing methods attract comparatively less interest and their advantages have not been fully explored. This paper proposes a post-processing scan chain watermarking scheme to incorporate the authorship proof into the scan path of an IP core generated by a Synthesis-for-Testability (SfT) approach. The SfT algorithm is firstly applied on the design to create an optimized scan chain. The scan chain is then partially reordered according to the watermarked constraints generated cryptographically by an authorship message. The watermark is embedded with little perturbation to the optimality already attained by the scan design. This has effectively addressed the unpredictable overhead of watermarking commonly encountered in preprocessing methods. Our method possesses similar robustness as the preprocessing methods. Experimental results on ISCAS´89 and LGSynth´93 benchmark circuits demonstrate that our proposed method causes lower fluctuations in area and timing overheads than the pre-processing SfT watermarking scheme.