An analysis of output ripples for PMOS charge pumps and design methodology

Author

Boy-Yiing Jaw ; Hongchin Lin

Author_Institution

Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan

fYear

2012

fDate

2-5 Dec. 2012

Firstpage

424

Lastpage

427

Abstract

An analysis of output ripples for PMOS charge pumps is presented. Since the on-resistance of switching transistor plays an important role, the analytical model including this effect is derived and extensively verified by simulations using the 0.35 μm CMOS technology with errors within 7%. The measurement results also agree with the simulations. Based on the model, the guidelines to select the boosting capacitors, on-die output filtering capacitor and the optimized transistor sizes at the output stage are proposed. It would be helpful to design reduced-ripple PMOS charge pumps with good power efficiency and high boosted voltages.

Keywords

CMOS integrated circuits; MOS integrated circuits; capacitors; charge pump circuits; CMOS technology; analytical model; boosted voltages; boosting capacitors; design methodology; design reduced-ripple PMOS charge pumps; on-die output filtering capacitor; on-resistance; optimized transistor sizes; output ripples; output stage; power efficiency; switching transistor; Capacitors; Charge pumps; Clocks; Integrated circuit modeling; Semiconductor device modeling; Transistors; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1728-4

Type

conf

DOI

10.1109/APCCAS.2012.6419062

Filename

6419062