Hardware implementation for fast convolution with a PN code using field programmable gate array

In a code division multiple access (CDMA) system, receivers spend a long time acquiring the signals. This is mostly due to the use of expensive FFT-based convolvers in the acquisition process. The paper shows a substitute algorithm for calculating the convolution that requires less computation time. The algorithm uses a Walsh transform instead of FFTs. The FFT-based algorithm requires 2 FFTs and one IFFT in addition to complex multiplications and additions. On the other hand, in the Walsh-based method the Walsh transform is required once and there is no multiplication. Therefore, using the Walsh-based algorithm can cut the processing time to about 5 percent of the required time. The additional steps in this algorithm are the permutation of the input samples and the output results. The design uses a field programmable gate array (FPGA) to apply a parallel processing concept. The paper discusses the algorithm and the implementation issues. A case study of a large code was carried out. The whole system has been implemented and showed high performance that speeds up the process to 2500 times the speed of a microprocessor based design