Title :
An entropy-based learning hardware organization using FPGA
Author :
Starzyk, Janusz ; Guo, Yongtao
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Ohio Univ., Athens, OH, USA
Abstract :
A neural network model with entropy-based evaluator called EBE is proposed. An FPGA based design that implements the EBE model is presented. The PCI bus interface including DMA transfer is embedded into the design. 8-bit test data is fed into the design to verify the correctness of the algorithm and its FPGA implementation
Keywords :
field programmable gate arrays; learning (artificial intelligence); logic design; neural nets; DMA transfer; FPGA; FPGA based design; PCI bus interface; entropy-based evaluator; entropy-based learning; neural network model; Algorithm design and analysis; Arithmetic; Artificial neural networks; Biological neural networks; Circuits; Computer architecture; Entropy; Field programmable gate arrays; Hardware; Training data;
Conference_Titel :
System Theory, 2001. Proceedings of the 33rd Southeastern Symposium on
Conference_Location :
Athens, OH
Print_ISBN :
0-7803-6661-1
DOI :
10.1109/SSST.2001.918519
