A layered QC-LDPC decoder architecture for high speed communication system

The performance of a high-throughput long-distance communication system such as an optical transmission system is limited by the Net Coding Gain (NCG) of the Forward Error Correction (FEC) system. Summarizing the previous research works, Low-Density Parity-Check (LDPC) codes form one of the most promising FEC schemes to be applied in high-throughput communication systems. Designing a practical channel coding scheme with high code rate, low complexity, high throughput and extremely low error floor has always been a very challenging problem. Quasi-cyclic low-density parity-check (QC-LDPC) codes have been promising candidates to fulfill the above requirements but the implementation issues remain. In this paper, we propose a layered QC-LDPC decoder architecture with high code rate, low complexity, high throughput and excellent error performance. The architecture has been implemented using FPGA and the error performance has been shown to be good.