DocumentCode
3058800
Title
A low-complexity high-performance wear-leveling algorithm for flash memory system design
Author
Ching-Che Chung ; Ning-Mi Hsueh
Author_Institution
Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
fYear
2012
fDate
2-5 Dec. 2012
Firstpage
595
Lastpage
598
Abstract
In this paper, a low-complexity high-performance wear-leveling algorithm which named sequential garbage collection (SGC) for flash memory system design is presented. The proposed SGC outperforms existing designs in terms of wear evenness and low design complexity. The lifetime of the entire flash memory can be greatly lengthened by the proposed SGC. In addition, the proposed SGC doesn´t require any tuning threshold parameter, and thus it can be applied to various systems without prior knowledge of the system environment for threshold tuning. The low-complexity low-cost SGC makes it is easy to be implemented by firmware-based or hardware-based approaches. The simulation results show that the maximum block erase count and the standard deviation of the block erase count are decreased by up to 75% and 94%, respectively, as compared to the greedy algorithm.
Keywords
flash memories; greedy algorithms; logic design; firmware-based approaches; flash memory system design; greedy algorithm; hardware-based approaches; low-complexity high-performance wear-leveling algorithm; maximum block erase count; sequential garbage collection; standard deviation; tuning threshold parameter; Algorithm design and analysis; Flash memory; Greedy algorithms; Heuristic algorithms; Standards; Tuning; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on
Conference_Location
Kaohsiung
Print_ISBN
978-1-4577-1728-4
Type
conf
DOI
10.1109/APCCAS.2012.6419105
Filename
6419105
Link To Document