• DocumentCode
    3058819
  • Title

    Modeling, simulation and verification of void transfer process for patterning nm scale features

  • Author

    Josan, Guriqbal Singh ; Kurinec, Santosh K.

  • Author_Institution
    Dept. of Microelectron. Eng., Rochester Inst. of Technol., Rochester, NY, USA
  • fYear
    2009
  • fDate
    9-11 Dec. 2009
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    The mainstay of this work is simulation and verification of a revolutionary void transfer process for nm scale features. In conclusion, the effects of geometrical factors on the void transfer process have been simulated using a modeling software and verified experimentally.
  • Keywords
    voids (solid); modeling software; void transfer process; CMOS technology; Educational institutions; Microelectronics; Optical films; Paper technology; Silicon compounds; Solid modeling; Space technology; Wet etching; X-ray lithography;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Device Research Symposium, 2009. ISDRS '09. International
  • Conference_Location
    College Park, MD
  • Print_ISBN
    978-1-4244-6030-4
  • Electronic_ISBN
    978-1-4244-6031-1
  • Type

    conf

  • DOI
    10.1109/ISDRS.2009.5378229
  • Filename
    5378229
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3058819