Memory binding and layer assignment for high-level synthesis of 3D ICs

In modern SOC design, communications between logic circuits and memories often become the bottlenecks of system performance. Among different types of memories, DRAM is especially suitable for large quantity of data storage. To reduce both the wire distance and bandwidth between logic circuits and DRAM modules, three dimensional integrated circuits (3D ICs) is one of the promising solutions. In this paper, we propose a K-L algorithm for memory binding and layer assignment of memory modules in high-level synthesis of 3D ICs. By the proposed memory binding technique, we can increase the number of row buffer hits for data accesses of DRAM modules, and hence improve the system performance. In addition, by the layer assignment of memory modules proposed in our algorithm, we can reduce the area of memory tier in the 3D ICs architectures. Experimental results show that our algorithm can balance the performance and hardware cost of memory accesses, and get a feasible solution for the tested benchmarks.