Fault tolerant maintenance networks for highly reliable WSI systems

The application of fault-tolerant network concepts, architectures, and evaluation techniques to dedicated built-in self-test (BIST) maintenance networks (MNets) for wafer scale integration (WSI) systems is described. In particular, the effects on overall WSI system reliability and performance due to wafer level maintenance network interconnection electromigration failures are evaluated. Three novel fault-tolerant MNet architectures are proposed based on loop and bus topologies. The reliability of WSI systems using existing and proposed MNet architectures is determined, and the results illustrate that there are substantial differences in useful system mission lifetimes. In addition, several new performance structures or metrics are proposed. The useful work obtained from these architectures can be grouped into two categories: those which are highly redundant and utilize distributed maintenance processors, and those less redundant architectures which use a single maintenance processor