DocumentCode :
3058990
Title :
Simultaneous wafer bonding type selection and layer assignment for TSV count minimization
Author :
Chun-Hua Cheng ; Wei-Shuo Tzeng ; Shih-Hsu Huang
Author_Institution :
Dept. of Electron. Eng., Chung Yuan Christian Univ., Chungli, Taiwan
fYear :
2012
fDate :
2-5 Dec. 2012
Firstpage :
627
Lastpage :
630
Abstract :
TSV (through-silicon-via) count minimization is one of the most important objectives in the three-dimensional integrated circuit (3D IC) design. In this paper, we demonstrate that, in addition to the layer assignment, the selection of wafer bonding type for each layer also has a great impact on TSV count minimization. However, to the best of our knowledge, up to now, no attention has been paid to the problem of selecting wafer bonding type for each layer. Based on that observation, we propose an integer linear programming (ILP) approach to formally draw up the simultaneous wafer bonding type selection and layer assignment for TSV count minimization. Note that our ILP approach guarantees obtaining the optimal solution. Compared with the previous high-level synthesis approach that uses ILP to minimize the TSV count (without considering the selection of wafer bonding type for each layer), experimental results show that our approach can further reduce 56.97% TSV count without any area overhead.
Keywords :
integer programming; integrated circuit design; linear programming; three-dimensional integrated circuits; wafer bonding; 3D IC design; ILP approach; TSV count minimization; integer linear programming; layer assignment; three-dimensional integrated circuit; through-silicon-via; wafer bonding type selection; Adders; Bonding; Metallization; Minimization; Substrates; Through-silicon vias; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4577-1728-4
Type :
conf
DOI :
10.1109/APCCAS.2012.6419113
Filename :
6419113
Link To Document :
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