Nanoscale TiN wet etching and its application for FinFET fabrication

Author

Liu, Y.X. ; Kamei, T. ; Endo, K. ; Uchi, S.O. ; Tsukada, J. ; Yamauchi, H. ; Hayashida, T. ; Ishikawa, Yozo ; Matsukawa, T. ; Sakamoto, K. ; Ogura, A. ; Masahara, M.

Author_Institution

Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST), Tsukuba, Japan

fYear

2009

fDate

9-11 Dec. 2009

Firstpage

1

Lastpage

2

Abstract

The nanoscale TiN wet etching and its application for FinFET fabrication have been systematically investigated. It is experimentally found that the TiN side-etching can be controlled to be half of TiN thickness with precise time control. By using the developed nanoscale TiN wet etching technique, sub-30-nm physical gate length FinFETs, 100-nm tall fin CMOS inverters and SRAM half-cells have successfully been fabricated. These experimental results indicate that the developed nanoscale TiN wet etching technique is very useful for the tall fin CMOS fabrication.

Keywords

MOSFET; etching; semiconductor device manufacture; titanium compounds; FinFET fabrication; SRAM half-cells; TiN; fin CMOS inverters; nanoscale wet etching; side-etching; size 100 nm; size 30 nm; Atherosclerosis; CMOS technology; Educational institutions; Fabrication; FinFETs; Materials science and technology; Plasma applications; Plasma measurements; Tin; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2009. ISDRS '09. International

Conference_Location

College Park, MD

Print_ISBN

978-1-4244-6030-4

Electronic_ISBN

978-1-4244-6031-1

Type

conf

DOI

10.1109/ISDRS.2009.5378248

Filename

5378248