Increasing the accuracy of statistical simulation for modeling superscalar processors

Statistical simulation is known to be a useful technique to efficiently cull huge design spaces in limited time due to its fast simulation property. Statistical simulation consists of modeling the execution of a computer program by a statistical profile and generating a synthetic trace from it. Current statistical simulation techniques use simple cache statistics producing a flat cache miss behaviour that does not resemble the bursty cache miss behaviour that is observed in real-life applications. We propose to model the burstiness of cache misses by using enhanced cache statistics that include distributions concerning the gaps between consecutive cache misses. For the data cache, we also model delayed hits. The improvements proposed are evaluated for wide-issue out-of-order architectures using SPECint95 and IBS traces