• DocumentCode
    3059598
  • Title

    Efficient Analysis of Fault Trees with Voting Gates

  • Author

    Xiang, Jianwen ; Yanoo, Kazuo ; Maeno, Yoshiharu ; Tadano, Kumiko ; Machida, Fumio ; Kobayashi, Atsushi ; Osaki, Takao

  • Author_Institution
    Service Platforms Res. Labs., NEC Corp., Kawasaki, Japan
  • fYear
    2011
  • fDate
    Nov. 29 2011-Dec. 2 2011
  • Firstpage
    230
  • Lastpage
    239
  • Abstract
    The voting gate, or k-out-of-n (k/n) gate, is a standard logic gate used in fault trees modelling fault-tolerant systems. It is traditionally expanded into a combination of AND and OR gates, and this expansion may result in combinatorial explosion problem in the calculation of minimal cut sets (MCSs) of the fault tree for even a not very big n, especially when the voting gate inputs are intermediate rather than basic events. In this paper we propose a set of reduction rules to simplify the voting gates without direct expanding, and also propose a concept of minimal cut vote (MCV) denoting a k/n gate whose inputs are all basic events and whose k-combinations are all MCSs of the fault tree. With the proposed reduction rules and MCV concept, the MCSs of fault trees can be evaluated and weeded more efficiently and the result can be represented in a more compact form. The results of experiments on practical fault trees with voting gates show that our method not only outperforms conventional MCS evaluation methods by several orders of magnitude but also provides performance comparably to that provided by binary decision tree (BDD) based algorithms.
  • Keywords
    decision trees; fault tolerant computing; fault trees; logic gates; AND gate; OR gate; binary decision tree based algorithms; combinatorial explosion problem; fault tree analysis; fault trees modelling fault-tolerant systems; k-out-of-n gate; minimal cut sets; minimal cut vote; reduction rules; standard logic gate; voting gates; Algorithm design and analysis; Boolean functions; Complexity theory; Data structures; Equations; Fault trees; Logic gates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Software Reliability Engineering (ISSRE), 2011 IEEE 22nd International Symposium on
  • Conference_Location
    Hiroshima
  • ISSN
    1071-9458
  • Print_ISBN
    978-1-4577-2060-4
  • Type

    conf

  • DOI
    10.1109/ISSRE.2011.23
  • Filename
    6132971