DocumentCode
3060103
Title
Fault Modeling and Analysis for Bridging Defects in a Synchronizer
Author
Kim, Hyoung-Kook ; Jone, Wen-Ben
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Cincinnati, Cincinnati, OH
fYear
2008
fDate
16-18 July 2008
Firstpage
397
Lastpage
403
Abstract
This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the syncronizer, and HSPICE is used to perform circuit analysis. The defects are exhaustively injected and simulated to find all possible faults that might occur in the synchronizer. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains.
Keywords
SPICE; flip-flops; integrated circuit modelling; network analysis; D flip-flops; HSPICE; bridging defects; circuit analysis; different clock domains; fault analysis; fault modeling; interfacing circuits; synchronizer; Circuit faults; Circuit simulation; Circuit testing; Clocks; Flip-flops; Frequency synchronization; Inverters; Metastasis; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Aerospace and Electronics Conference, 2008. NAECON 2008. IEEE National
Conference_Location
Dayton, OH
ISSN
7964-0977
Print_ISBN
978-1-4244-2615-7
Electronic_ISBN
7964-0977
Type
conf
DOI
10.1109/NAECON.2008.4806580
Filename
4806580
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